1. Field of the Invention
The present invention relates to a semiconductor device and a testing apparatus thereof. More particularly, the present invention relates to a semiconductor device which performs a prescribed operation in synchronization with a clock signal and a testing apparatus thereof.
2. Description of the Background Art
FIG. 29 is a circuit block diagram showing a structure of a conventional dynamic random access memory (hereinafter referred to as DRAM) chip. Referring to FIG. 29, this DRAM chip includes a power supply terminal 201, a ground terminal 202, an internal timer 203 and an internal circuit 204. Internal timer 203 and internal circuit 204 both receive a power supply potential Vcc and a ground potential GND externally through power supply terminal 201 and ground terminal 202. Internal timer 203 includes a self-oscillating oscillator such as a ring oscillator, and applies a clock signal .phi. with a prescribed frequency to internal circuit 204. Internal circuit 204 performs a prescribed operation (for example, refresh operation) in synchronization with that clock signal .phi..
In the conventional DRAM chip, however, there has been a problem that the value of the frequency of the clock signal .phi. would be offset from the originally set value due to inconstancy in manufacturing such that desired operation characteristics cannot be obtained. For example, when the frequency of the clock signal .phi. becomes unnecessarily high, power dissipation would increase to an unwanted extent or there would be erroneous operation in the system including DRAM because the internal circuit 204 cannot interlock with the external components. However, even a means for drawing the clock signal .phi. externally to measure its frequency was not provided in the conventional DRAM chip.